In a semiconductor test process, a wafer level test for detecting a defective product is sometimes performed by performing a conductivity test by bringing probes having conductivity (conductive probes) into contact with a semiconductor wafer before dicing. When the wafer level test is performed, to transfer a signal for a test generated and sent by a testing device (tester) to the semiconductor wafer, a probe card housing a large number of probes is used. In the wafer level test, the probes are individually brought into contact with each of dies on the semiconductor wafer while the dies are scanned by the probe card. However, because hundreds to tens of thousands of dies are formed on the semiconductor wafer, it takes considerable time to test one semiconductor wafer. Thus, an increase in the number of dies causes higher cost.
To solve the problems of the wafer level test, in recent years, a method called full wafer level test is also used in which hundreds to tens of thousands of probes are collectively brought into contact with all or at least about ¼ to ½ of dies on a semiconductor wafer. To accurately bring the probes into contact with the semiconductor wafer, this method requires a technology for accurately keeping the parallelism or the flatness of a probe card with respect to a predetermined reference surface. For example, Patent Document 1 described below discloses a technology related to a clamp frame that presses an edge portion of a space transformer that spatially widens the interval of fine wires of probes as part of a mechanism for flattening a wiring substrate.    Patent Document 1: Japanese Patent Application Laid-open No. 2005-164601 (FIG. 1)